This invention relates to the field of semiconductor manufacture and, more particularly, to a double-sided capacitor structure and a method for forming the structure.
During the manufacture of semiconductor devices which comprise memory elements, such as dynamic random access memories (DRAMs), static random access memories (SRAMs), and some microprocessors, container capacitors are commonly formed. Container capacitors are well known to allow an increased stored charge over planar capacitors by increasing the surface area on which the charge can be stored. To further increase the surface area on which the charge can be stored, polysilicon storage nodes are commonly converted to hemispherical silicon grain (HSG) polysilicon. This material has a roughened surface compared with non-HSG polysilicon, and therefore an increased surface area on which a charge can be stored.
FIGS. 1-8 depict a conventional method for forming a container capacitor from HSG polysilicon. FIG. 1 depicts a semiconductor wafer substrate assembly 10 comprising a semiconductor wafer 12 having a plurality of doped areas 14 which allow proper operation of a plurality of transistors 16. Each transistor comprises gate oxide 18, a doped polysilicon control gate 20, silicide 22 such as tungsten silicide to increase conductivity of the control gate, and a capping layer 24 of tetraethyl orthosilicate (TEOS) oxide. Silicon nitride spacers 26 insulate the control gate 20 and silicide 22 from polysilicon pads 28 to which the container capacitors will be electrically coupled. Further depicted in FIG. 1 is shallow trench isolation (STI, field oxide) 30 which reduces unwanted electrical interaction between adjacent control gates, and a thick layer of deposited oxide 32 such as borophosphosilicate glass (BPSG). A patterned photoresist layer 34 defines the location of the container capacitors to be formed. The FIG. 1 structure may further include one or more bit (digit) lines under the TEOS layer or various other structural elements or differences which, for simplicity of explanation, have not been depicted.
The FIG. 1 structure is subjected to an anisotropic etch which removes the exposed portions of the BPSG layer to form a patterned BPSG layer which provides a base dielectric having a recess for the container capacitor. During this etch the polysilicon pads 28 and possibly a portion of TEOS capping layer 24 are exposed as depicted in FIG. 2. The remaining photoresist layer is stripped and any polymer (not depicted) which forms during the etch is removed according to means known in the art to provide the FIG. 3 structure.
As depicted in FIG. 4, a blanket polysilicon layer 40 is formed conformal with the deposited oxide layer, and will provide a container capacitor storage node for the completed capacitor. A thick blanket filler material 42, such as photoresist, is formed to fill the containers provided by polysilicon 40. The FIG. 4 structure is then subjected to a planarizing process, such as a chemical planarization, a mechanical planarization, or a chemical mechanical planarization (CMP) step. This process removes horizontal portions of the photoresist 42, the polysilicon 40, and likely a portion of the BPSG 32 to result in the FIG. 5 structure.
Next, the BPSG 32 is partially etched with an etch selective to polysilicon (i.e. an etch which minimally etches or, preferably, doesn""t etch polysilicon) to result in the structure of FIG. 6. At this point in the process the polysilicon storage nodes 40 are only minimally supported. The bottom plates 40 in the FIG. 6 structure each comprise a first region 60 which defines a recess, and a second region 62 which defines an opening to the recess, with the first and second regions being continuous, each with the other. In other words, the bottom plate 40 of FIG. 6 defines a receptacle having a rim 62 which defines an opening to the interior of the receptacle. The regions 60, 62 form vertically-oriented sides of the bottom plate, and the sides are electrically-coupled by a horizontally-oriented bottom 64.
After etching the BPSG, a process is performed which converts the smooth polysilicon to HSG polysilicon storage plates 70 as depicted in FIG. 7. Various processes for converting the smooth polysilicon to HSG polysilicon are known in the art.
After performing the conversion of the smooth polysilicon to HSG polysilicon, a cell dielectric layer 80, for example a layer of high-quality cell nitride, a polysilicon container capacitor top plate 82, and a planar oxide layer such as BPSG 84 are formed according to means known in the art to result in the FIG. 8 structure. Subsequently, wafer processing continues according to means known in the art.
One problem which can result during the process described above is flaking of the HSG polysilicon from the storage node 70 as depicted in FIG. 9. These loose portions 90 are conductive and thus, when they break off and contact two adjacent conductive structures, can short the structures together and result in a malfunctioning or nonfunctioning device. Typically, the greatest number of such defect occurs at the top of the storage plates. This may occur as these ends are not protected by adjacent structures. This may also occur because as wafer processing continues the tops are the most likely portion of the storage plate to be contacted during a CMP or other step, and also incur the highest stresses.
Another problem which can occur with the process described above results from the very close lateral spacing between adjacent storage plates. As a design goal of semiconductor engineers is to form as many storage capacitors per unit area as possible, and there are typically several million storage capacitors on each memory chip, even a small decrease in spacing between features can allow for the formation of many more features in the same area. Thus the capacitors are formed as close together as wafer processing will allow. As the roughened polysilicon grains grow, grains from two adjacent plates can form a bridge 92 between the two plates and thus short them together to result in a malfunctioning device.
Forming the capacitor structures close together such that there is very little space between adjacent double-sided containers also makes it likely that particles of contamination will be trapped between adjacent containers to result in shorting between the containers. Given the normally tight and deep spaces of the structure, it is difficult or impossible to reliably remove the particles which contaminate the wafer surface with conventional cleaning steps currently available in the field of semiconductor device manufacturing.
A method used to form container capacitor storage plates which reduces or eliminates the problems described above, and a structure resulting therefrom, would be desirable.
The present invention provides a new method which, among other advantages, reduces problems associated with the manufacture of semiconductor devices, particularly problems resulting during the formation of double-sided capacitor structures (i.e. capacitor structures having the capacitor top plate formed on two sides of the bottom plate, the inside and the outside of the container, as depicted in FIG. 8). In accordance with one embodiment of the invention an opening is provided in an oxide layer and a first continuous polysilicon layer is formed within the opening. The first polysilicon layer is planarized, for example using a mechanical or chemical mechanical polishing (CMP) process. The first polysilicon layer, which will form a portion of the capacitor top plate, is then etched to form a plurality of recesses therein.
After forming the plurality of recesses in the first polysilicon layer, a blanket cell dielectric layer and a blanket second polysilicon layer are formed within the recesses. The second polysilicon and the cell dielectric are cleared from horizontal surfaces, including the upper surface of the first polysilicon layer. As the second polysilicon layer provides a seed layer for a roughened or textured layer such as a hemispherical silicon grain (HSG) polysilicon layer, the second polysilicon layer is converted to HSG polysilicon. Subsequently, the upper surface of the structure is planarized to remove the polysilicon from the surface, then the first and second polysilicon layers are recessed within the oxide using an etch selective to oxide (i.e. an etch which minimally etches or, preferably, does not etch oxide during etching of the polysilicon). A second cell dielectric layer is formed, and a third polysilicon layer is provided over the second cell dielectric layer, and within the recess formed in the plurality of recesses in the first polysilicon layer, which will form a second capacitor top plate layer.
After forming the second top plate layer, the first and second top plate layers are electrically coupled. Wafer processing continues according to means known in the art.
Using this process the highest defect source for HSG flaking is removed as a flaking source, which results in decreased device defects. Various embodiments of the inventive method, and an inventive structure resulting from the method, are described.